
`include "defines.v"
/* verilator lint_off LATCH */
//----------------------------------------------------------------
//Module Name : cpu_ctrl_id.v
//Description of module:
//control signal genaration 
//----------------------------------------------------------------
//Designer:	Tang Pengyu
//Date: 2021/07/22	  
//----------------------------------------------------------------

module	cpu_ctrl_exe(
		input	[7:0]	inst_opcode,
//		input	branch_eq,
//		input	branch_ne,
//		input	branch_lt,
//		input	branch_ge,
//		input	branch_ltu,
//		input	branch_geu,
		input	[63:0] ram_addr,
//		input	time_intr_r,			//中断响应
		input	[63:0] load_store_addr,			//exe_data
		
//		input	[6:0]	funct7,
		
		input	if_fetched,	
		
		output	load_mem_en,
		
		output	load_axi_en,
		output	reg load_clint_en,
		output	store_axi_en,
		output	reg store_clint_en,
		output	store_mem_en
//		output	[1:0] wb_sel
//		output	reg [63:0] store_mask
);

//inst_lb,inst_lbu	,inst_lh,inst_lhu,inst_lw,inst_lwu,inst_ld
assign load_mem_en = (inst_opcode == 8'b000_00000) | (inst_opcode == 8'b100_00000)
					| (inst_opcode == 8'b001_00000) | (inst_opcode == 8'b101_00000)
					| (inst_opcode == 8'b010_00000) | (inst_opcode == 8'b110_00000)
					| (inst_opcode == 8'b011_00000);
assign	load_axi_en = load_mem_en & (~load_clint_en);
assign	store_axi_en = store_mem_en & (~store_clint_en);		
//load_clint_en,store_clint_en
wire	clint_lock;
assign	clint_lock = if_fetched;
always @(*)	begin
	if(clint_lock == 1'b1)	begin
		load_clint_en = load_mem_en & 
			((load_store_addr == 64'h0000_0000_0200_bff8) | (load_store_addr == 64'h0000_0000_0200_4000));
		store_clint_en = store_mem_en &
			((load_store_addr == 64'h0000_0000_0200_bff8) | (load_store_addr == 64'h0000_0000_0200_4000));

	end
end	
/*
always @(*)
  begin
	case(inst_opcode)
		8'b000_01000:	store_mask = (ram_addr[2:0] == 3'b000) ? 64'h0000_0000_0000_00ff :
									(ram_addr[2:0] == 3'b001) ? 64'h0000_0000_0000_ff00 :
									(ram_addr[2:0] == 3'b010) ? 64'h0000_0000_00ff_0000 :
									(ram_addr[2:0] == 3'b011) ? 64'h0000_0000_ff00_0000 :
									(ram_addr[2:0] == 3'b100) ? 64'h0000_00ff_0000_0000 :
									(ram_addr[2:0] == 3'b101) ? 64'h0000_ff00_0000_0000 :
									(ram_addr[2:0] == 3'b110) ? 64'h00ff_0000_0000_0000 :
									(ram_addr[2:0] == 3'b111) ? 64'hff00_0000_0000_0000 : 64'd0;			//sb
		8'b001_01000:	store_mask = (ram_addr[2:0] == 3'b000) ? 64'h0000_0000_0000_ffff :
									(ram_addr[2:0] == 3'b001) ? 64'h0000_0000_00ff_ff00 :
									(ram_addr[2:0] == 3'b010) ? 64'h0000_0000_ffff_0000 :
									(ram_addr[2:0] == 3'b011) ? 64'h0000_00ff_ff00_0000 :
									(ram_addr[2:0] == 3'b100) ? 64'h0000_ffff_0000_0000 :
									(ram_addr[2:0] == 3'b101) ? 64'h00ff_ff00_0000_0000 :
									(ram_addr[2:0] == 3'b110) ? 64'hffff_0000_0000_0000 : 64'd0;			//sh
		8'b010_01000:	store_mask = (ram_addr[2:0] == 3'b000) ? 64'h0000_0000_ffff_ffff :
									(ram_addr[2:0] == 3'b001) ? 64'h0000_00ff_ffff_ff00 :
									(ram_addr[2:0] == 3'b010) ? 64'h0000_ffff_ffff_0000 :
									(ram_addr[2:0] == 3'b011) ? 64'h00ff_ffff_ff00_0000 :
									(ram_addr[2:0] == 3'b100) ? 64'hffff_ffff_0000_0000 : 64'd0;			//sw
		8'b011_01000:	store_mask = 64'hffff_ffff_ffff_ffff;			//sd
		default:		store_mask = 64'h0000_0000_0000_0000;
	endcase
  end
*/

assign store_mem_en = (inst_opcode == 8'b000_01000) | (inst_opcode == 8'b001_01000)
					| (inst_opcode == 8'b010_01000) | (inst_opcode == 8'b011_01000);			//sb,sh,sw,sd	


endmodule					